The present invention relates to integrated circuits and to methods for manufacturing them.
In a new class of integrated circuit fabrication processes taught by the grandparent application Ser. No. 729,318, filed May 1, 1985, pending, a very novel local interconnect technology was set forth, which resulted in very conveniently produced titanium nitride local interconnect line. These lines can be routed to interconnect p+ substrate regions, n+ substrate regions, and polysilicon in any pattern desired, while also permitting self-sligned silicidation to occur to clad surfaces of exposed silicon substrate areas and also of exposed polysilicon lines with silicide, to improve their conductivity.
In conventional processes for making dynamic random-access memories (DRAMs), the memory cells are formed using two separate polysilicon layer. The first layer is typically used for the gate of the pass transistor, and the second layer is typically used for the top plate of the storage capacitor.
Since thin film deposition steps and patterned etching steps are both significantly expensive process steps, it would be hghly desirable to be able to fabricate such devices with a reduced number of polysilicon deposition and etching steps. This would provide reduced fabrication cost, which is most especially important in such "commodity" parts.
The present invention provides a replacement for the capacitor technology typically used in many analog circuits in the prior art. (The capacitor technology provided by the present invention can also be used for the storage capacitors in DRAM memories, and also for other purposes such as bootstrapping capacitors in DRAM memories.) In the process normally used for fabricating circuits with large capacitors, a first thin film conductor layer (typically polysilicon) is used for the bottom plates of capacitors, and a second thin film conductive layer (typically also polysilicon, sometimes clad with a silicide) is used for the top plate of capacitors and is also used for the gates of MOS devices. Another class of embodiments of the present invention teaches that a single layer containing silicon--in particular, a single layer which consists essentially of silicon at its bottom boundary, to provide the advantageous electrical properties of a silicon/dielectric interface--is used for the bottom plate of capacitors and also for the gates of insulated gate field effect transistors. A titanium nitride thin film interconnect layer is used for the top plates of capacitors, and preferably also for local interconnect. The portions of the thin film titanium nitride layer which are used for local interconnect can link polysilicon, silicides, and crystalline silicon of any dopant level in any pattern desired. Again, this innovation provides improved topography and also simpler fabrication, resulting in higher yield and lower cost.
The TiN layer used also advantageously fits into other parts of the process. For example, another advantageous use of the TiN layer is to provide pads at the bottom of contact holes. Since the oxide etch chemistries normally used for contact etching are somewhat selective to TiN, this layer provides some protection against overetching when the contact wtch step must etch contact holes of various thickness. In particular, the present invention makes it easier to etch contact holes to substrate and to the polysilicon layer simultaneously. Moreover, the TiN etch stop pads can be extended from the source/drain regions (in the moats) up onto the field oxide, so that the contact hole does not have to fall within the perimeter of the source/drain, but can overlap up onto the field oxide. This means that the source/drain patterns can be drawn smaller, providing a further advantage of the invention.
Yet another use of the TiN layer provided by the presently preferred embodiments of the present invention is to provide capacitors to substrate. Since the interlevel dielectric is patterned after the source/drain implants, these capacitors can be located over heavily doped diffusions, so their parasitic series resistance should not be large.
Yet another use of the TiN layer provided by the presently preferred embodiments of the present invention is to provide Schottky diodes to substrate. By screening the source/drain implant from some areas of bare silicon, the TiSi.sub.2 /TiN layer formed on these areas will provide usable Schottky diodes.
Another way to regard advantages is that the present invention provides a tremendous step forward in process versatility.
One aspect of this is that the present invention units two objectives which had been separately pursued in the prior art, and resolves a dichotomy regarding specific capacitance: as integrated circuits are inexorably pushed toward higher operating speeds, it is desirable to reduce parasitic capacitances, and particularly interlevel parasitic capacitances (which can not only generally degrade speed, but also induce logic faults by coupling level transitions between adjacent conductors). However, while interlevel specific capacitance is generally sought to be minimized, there are many circuits (both analog and digital) where high specific capacitance is needed, in order to configure a capacitor in a reasonable area. The present invention resolves this dichotomy in two ways: a double contact etch is used to provide high-specific capacitance areas to the overlying conductor, and (optionally, in combination with this double contact etch) a single clad polysilicon level is split in some locations to provide a high interlevel specific capacitance, and united in other locations to provide low sheet resistance and low parasitic capacitance.
According to the present invention there is provided: A process for fabricating integrated circuits, comprising the steps of: providing a substrate having monocrystalline semiconductor portions at least some surface portions thereof, said semiconductor consisting predominantly of silicon; providing device isolation areas in a predetermined pattern to define separate moat regions in predetermined locations of said monocrystalline semiconductor; fabricating insulated gate field effect transistors in predetermined locations in said moat regions, gates of said insulated gate field effect transistors being formed by portions of a first patterned thin film conductive layer; providing a first capacitor dielectric over at least some parts of said first patterned thin film conductive layer; depositing a metal consisting substantially of titanium overall; heaving said substrate and said metal in a nitrogen-bearing atmosphere, so that said metal reacts with exposed portions of said substrate to form titanium silicides, and other portions of said metal also react with said nitrogen atmosphere to form a layer having a large fraction of titanium nitride at the surface thereof; and etching predetermined locations of said titanium nitride layer to provide local interconnection in a predetermined pattern, while also leaving portions of said titanium nitride layer in place over at least some locations of said first capacitor dielectric over said first patterned thin film conductive layer in predetermined capacitor locations; providing an interlevel dielectric substantially covering said active devices and said capacitor locations; removing first portions of said interlevel dielectric to expose at least some of said capacitor locations, and depositing a second capacitor dielectric; removing second portions of said interlevel dielectric to expose predetermined ohmic contact locations; and depositing and etching a metal to define a thin film metal interconnect layer in a predetermined configuration, and to define insulated capacitor top plates over ones of said capacitor locations.
According to the present invention there is also provided: An integrated circuit device comprising: a substrate; device isolation regions defining predetermined moat areas of exposed semiconducting material; a plurality of active devices near the surface of said moat areas, portions of said active devices above the surface of said semiconducting areas of said moat being formed from a first thin film conductive layer which is polycrystalline and comprises more than 30% atomic of silicon; a local interconnect layer comprising a patterned thin film consisting substantially of titanium nitride, portions of said local interconnect layer making ohmic contact, in accordance with a predetermined electrical circuit configuration, to respective portions of said active devices; a patterned thin film metal interconnect layer, portions of said metal layer making ohmic contact, in accordance with a predetermined electrical circuit configuration, to respective portions of said active devices; and one or more capacitors, ones of said capacitors each comprising a first plate, comprising a respective portion of said first thin film conductive layer, a second plate, overlying and insulated from said first plate, comprising a respective portion of said patterned local interconnect thin film layer, and a third plate, overlying and insulated from said second plate, comprising a respective portion of said metal interconnect layer.